Memory read, erase or program operations are conventionally executed in response to external signals provided to the memory by a controller (not shown) or other memory access device (also not shown). A bit line coupled to a selected memory cell to be read, erased or programmed must be pre-charged or prepared for executing a particular memory operation. FIG. 1 shows a block diagram of a prior art bit line driver 101 coupled to a bit line of a memory array. The bit line driver 101 is designed to meet a number of operating requirements during a memory operation. For example, during a programming operation, the bit line driver 101 receives data to be programmed to a selected memory cell, and applies the programming data signal to the bit line. Memory having multi-level cells require multiple programming voltages and/or programming pulse widths corresponding to combinations of the multiple data bits that can be stored in the memory cell.
An input data bit received by the memory device are applied to an inverter 105 through an NMOS transistor 103 that is continuously turned ON by a supply voltage Vcc coupled to its gate. The output signal of the inverter 105 is applied to a node 115 through an NMOS bias transistor 110 that receives a predetermined bias voltage. A number of components are coupled to the node 115 to allow the bit line driver 101 to perform several functions. The node 115 is coupled to the corresponding bit line by an NMOS transistor 119, and also through an NMOS transistor 117 to an output of an inverter 125, which precharges the node 115 to a voltage Vcc or Vss depending on a voltage applied to the input of the inverter 125. The respective gates of the transistors 117, 119 are coupled to an output of an inverter 123 so that both transistors 117, 119 are turned ON responsive to a low applied to the input of the inverter 123. The output node 115 is also coupled to a state machine through an inverter 121 that communicates signals to the state machine during programming operations. For example, the state machine may receive an instruction set to program a particular block of memory. In response, the state machine signals the bit line driver 101 to precharge the bit line or it may cause a predetermined programming voltage to be applied to the selected bit line during a programming operation.
In operation, the manner in which the bit line driver 101 responds to the input data bit depends upon the initial state of the output node 115. For example, the state machine may interpret a low at the output of the inverter 121 as indicating that a program operation is needed to change the state of a memory cell being programmed. Thus, if the output node 115 is initially at VCC, an active operation occurs in which the input data bit applied to the inverter 105 controls the state of the output node 115. Therefore, if the input data bit is high, the output node 115 will be pulled to the low (VSS) at the output of the inverter 105 through the transistor 110, which is turned ON by the bias voltage. If the input data bit is low, the output of the inverter 105 will by high. In such case, the transistor 110 will be turned OFF. Although the inverter 105 will be unable to drive the output node 115 high, the output node 115 will nevertheless remain high because of the charge on a capacitor 107 that is coupled to the output node 115.
If the state machine interprets a low at the output of the inverter 121 as calling for an active operation, it may interpret a high at the output of the inverter 121 as calling for a null operation in which the input data applied to the inverter 105 does not control the state of the output node 115. In the case of a null operation, the output node 115 will initially be discharged to VSS. If the input data bit is high, the output of inverter 105 will be low, and the output node 115 will therefore remain at VSS. Finally, if the input data bit is low, the output of the inverter 105 will be high. The transistor 110 will be turned ON by the bias voltage to allow the output of the inverter 105 to charge the output node 115. However, the voltage of the output node 115 will increase only until it reaches the bias voltage less the threshold voltage of the transistor 110, at which point the transistor 110 will turn OFF. By choosing the magnitude of the bias voltage so that it is substantially equal to VT−VSS, where VT is the threshold voltage of the transistor 110, the output node 115 will remain at VSS, thereby continuing to indicate a null operation to the state machine. Thus, by keeping the magnitude of the bias voltage at substantially equal to VT−VSS, the bit line driver 101 can maintain the proper voltage on the output node 115 for all values of the input data bit in both the active operation and the null operation. The operation of the bit line driver 101 for both values of input data bits in the active operation and the null operation are summarized in Table 1, below:
TABLE 1Initial StateInputFinal Stateof Node 115Dataof Node 115Case #1Vcc1VssCase #2Vcc0VccCase #3Vss1VssCase #4Vss0Vss
Unfortunately, it is difficult to maintain the bias voltage at the correct magnitude since the bias voltage can vary significantly with different process variations and as the temperature of the integrated circuit substrate varies. As a result, the voltage of the output node 115 can rise to unacceptable levels in the null operation when the input data bit is low. More specifically, if the voltage of the output node 115 increases above the threshold voltage of an NMOS transistor (not shown) in the inverter 121, the NMOS transistor and a complementary PMOS transistor (not shown) connected in series with the NMOS transistor will both be ON at the same time. Insofar as a bit line driver 101 is provided for each column of a memory device, the amount of power consumed by the transistors in the inverter 121 can be considerable. Also, in some cases, the inverter 121 may apply a signal to the state machine that incorrectly calls for an active operation.
There is, therefore, a need for a bit line driver in a non-volatile memory device and method for generating a bias voltage that ensures the correct operation of the bit line driver for all operating conditions despite process and temperature variations.